View VND830LSP_7577866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

october 2010 doc id 9431 rev 4 1/27 1 VND830LSP double channel high-side driver features cmos compatible inputs open drain status outputs on-state open-load detection off-state open-load detection shorted load protection undervoltage and overvoltage shutdown loss of ground protection very low standby current reverse battery protection description the VND830LSP is a monolithic device designed using | stmicroelectronics? vipower? m0-3 technology. the VND830LSP is intended for driving any type of multiple load with one side connected to ground. the active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility ta ble). active current limitation combined with thermal shutdown and automatic restart protects the device against overload. the open-load threshold is aimed at detecting the 5 w / 12 v standard bulb as an open-load fault in the on-state. the device detects the open-load condition in both the on and off-state. in the off-state the device detects if the output is shorted to v cc . the device automatically turns off in the case where the ground pin becomes disconnected. type r ds(on) i out v cc VND830LSP 60 m (1) 1. per each channel. 18 a (1) 36 v powerso-10 1 10 table 1. device summary package order codes tube tape and reel powerso-10 VND830LSP VND830LSP13tr www.st.com
contents VND830LSP 2/27 doc id 9431 rev 4 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16 3.1.1 solution 1: a resistor in the ground line (rgnd only) . . . . . . . . . . . . . . 16 3.1.2 solution 2: a diode (d gnd ) in the ground line . . . . . . . . . . . . . . . . . . . . 17 3.2 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 mcu i/o protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 maximum demagnetization energy (v cc = 13.5 v) . . . . . . . . . . . . . . . . . 19 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 powerso-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 powerso-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 powerso-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VND830LSP list of tables doc id 9431 rev 4 3/27 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. v cc - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. switching (v cc = 13 v; t j = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 9. logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 10. status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 11. open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 12. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 13. electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 14. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. powerso-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of figures VND830LSP 4/27 doc id 9431 rev 4 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. i lim vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. on-state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 16. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 17. on-state resistance vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 18. input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 19. status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 20. status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 21. status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 22. open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 23. open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 24. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 25. open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 26. maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 27. powerso-10 pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 28. r thj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20 figure 29. thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 30. thermal fitting model of a double channel hsd in powerso-10 . . . . . . . . . . . . . . . . . . . . 21 figure 31. powerso-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 32. powerso-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 33. powerso-10 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 34. powerso-10 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VND830LSP block diagram and pin description doc id 9431 rev 4 5/27 1 block diagram and pin description figure 1. block diagram figure 2. configurati on diagram (top view) table 2. suggested connections for unused and not connected pins connection / pin status n.c. output input floating x x x x to ground x through 10k resistor overtemp. 1 v cc gnd input1 output1 overvoltage logic driver 1 status1 v cc clamp undervoltage clamp 1 open load on 1 current limiter 1 open load off 1 output2 driver 2 clamp 2 open load on 2 open load off 2 overtemp. 2 input2 status2 current limiter 2 1 2 3 4 5 6 7 8 9 10 11 output 1 output 1 n.c. output 2 output 2 ground input 1 status 1 status 2 input 2 v cc
electrical specifications VND830LSP 6/27 doc id 9431 rev 4 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality document. table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r = 1.5 k ; c=100pf) ?input ?status ?output ?v cc 4000 4000 5000 5000 v v v v e max maximum switching energy (l = 0.14 mh; r l = 0 ; v bat = 13.5 v; t jstart = 150 c; i l =14a) 52 mj p tot power dissipation (per island) at t lead =25c 74 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 t stg storage temperature - 55 to 150 c
VND830LSP electrical specifications doc id 9431 rev 4 7/27 2.2 thermal data 2.3 electrical characteristics values specified in this section are for 8 v < v cc < 36 v; -40 c < t j < 150 c, unless otherwise stated. figure 3. current and voltage conventions table 4. thermal data (per island) symbol parameter value unit r thj-lead thermal resistance junction-lead 2 c/w r thj-amb thermal resistance junction-ambient 52 (1) 1. when mounted on a standard single-sided fr-4 board with 0.5 cm 2 of cu (at least 35 m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. 37 (2) 2. when mounted on a standard single-sided fr-4 board with 6 cm 2 of cu (at least 35 m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. c/w i s i gnd output 2 v cc gnd status 2 input 2 i out2 i in2 i stat2 v stat2 v in2 v cc v out2 output 1 i out1 v out1 input 1 i in1 status 1 i stat1 v in1 v stat1 v f1 (*) note: v fn = v ccn - v outn during reverse battery condition.
electrical specifications VND830LSP 8/27 doc id 9431 rev 4 note: to ensure long term reliability under heavy ov erload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. table 5. power output symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 5.5 13 36 v v usd undervoltage shutdown 3 4 5.5 v v ov overvoltage shutdown 36 v r on on-state resistance i out = 2a; t j = 25c i out = 2a; v cc > 8v 60 120 m m i s supply current off-state; v cc = 13 v; v in = v out = 0 v 12 40 a off-state; v cc = 13 v; v in = v out = 0 v; t j = 25 c 12 25 a on-state; v cc = 13 v; v in = 5 v; i out = 0 a 57ma i l(off1) off-state output current v in = v out = 0 v 0 50 a i l(off2) off-state output current v in = 0v; v out = 3.5 v -75 0 a i l(off3) off-state output current v in = v out = 0 v; v cc = 13 v; t j = 125 c 5a i l(off4) off-state output current v in = v out = 0 v; v cc = 13 v; t j = 25 c 3a table 6. protections symbol parameter test conditions min. typ. max. unit t tsd shutdown temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload conditions t j > t tsd 20 s i lim current limitation v cc = 13 v 18 23 29 a 5.5 v < v cc < 36 v 29 a v demag turn-off output clamp voltage i out = 2a; l = 6mh v cc - 41 v cc - 48 v cc - 55 v
VND830LSP electrical specifications doc id 9431 rev 4 9/27 table 7. v cc - output diode symbol parameter test conditions min. typ. max. unit v f forward on voltage - i out = 1.3 a; t j = 150 c ? ? 0.6 v table 8. switching (v cc = 13 v; t j = 25 c) symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l = 6.5 from v in rising edge to v out = 1.3 v (see figure 5 ) 53060s t d(off) turn-off delay time r l = 6.5 from v in falling edge to v out = 11.7 v (see figure 5 ) 10 30 70 s dv out /dt (on) turn-on voltage slope r l = 6.5 from v out = 1.3 v to v out = 10.4 v (see figure 5 ) 0.15 see figure 10 1.5 v/s dv out /dt (off) turn-off voltage slope r l = 6.5 from v out = 11.7 v to v out = 1.3 v (see figure 5 ) 0.1 see figure 12 0.75 v/s table 9. logic inputs symbol parameter test conditions min. typ. max. unit v il input low level 1.25 v i il low level input current v in = 1.25 v 1 a v ih input high level 3.25 v i ih high level input current v in = 3.25 v 10 a v i(hyst) input hysteresis voltage 0.5 v v icl input clamp voltage i in = 1 ma 6 6.8 8 v i in = -1 ma -0.7 v table 10. status pin symbol parameter test conditions min. typ. max. unit v stat status low output voltage i stat = 1.6 ma 0.5 v i lstat status leakage current normal operation; v stat = 5v 10 a c stat status pin input capacitance normal operation; v stat = 5v 100 pf v scl status clamp voltage i stat = 1 ma 6 6.8 8 v i stat = - 1 ma -0.7 v
electrical specifications VND830LSP 10/27 doc id 9431 rev 4 figure 4. status timings figure 5. switching time waveforms table 11. open-load detection symbol parameter test conditions min. typ. max. unit i ol open-load on-state detection threshold v in = 5 v 0.6 0.9 1.2 a t dol(on) open-load on-state detection delay i out = 0 a 200 s v ol open-load off-state voltage detection threshold v in = 0 v 1.5 2.5 3.5 v t dol(off) open-load detection delay at turn-off 1000 s v inn v statn t dol(off) open load status timing (with external pull-up) v inn v statn over temp status timing t sdl t sdl i out < i ol v out > v ol t dol(on) t j > t tsd
VND830LSP electrical specifications doc id 9431 rev 4 11/27 table 12. truth table conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l table 13. electrical transient requirements iso t/r 7637/1 test pulse test level i ii iii iv delays and impedance 1- 25v (1) 1. all functions of the device are performed as designed after exposure to disturbance. - 50v (1) - 75v (1) - 100v (1) 2ms, 10 2 + 25v (1) + 50v (1) + 75v (1) + 100v (1) 0.2ms, 10 3a - 25v (1) - 50v (1) - 100v (1) - 150v (1) 0.1s, 50 3b + 25v (1) + 50v (1) + 75v (1) + 100v (1) 0.1s, 50 4- 4v (1) - 5v (1) - 6v (1) - 7v (1) 100ms, 0.01 5+ 26.5v (1) + 46.5v (2) 2. one or more functions of the device is not perfor med as designed after exposure and cannot be returned to proper operation without replacing the device. + 66.5v (2) + 86.5v (2) 400ms, 2
electrical specifications VND830LSP 12/27 doc id 9431 rev 4 figure 6. waveforms open load without external pull-up status n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc v cc > v ov status input n status n status n input n status n input n open load with external pull-up undefined overtemperature input n status n t tsd t r t j load voltage n v cc v ol v ol
VND830LSP electrical specifications doc id 9431 rev 4 13/27 2.4 electrical char acteristics curves figure 7. off-state output current figure 8. high level input current figure 9. input clamp voltage figure 10. turn-on voltage slope figure 11. overvoltage shutdown figure 12. turn-off voltage slope -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 1.35 il(off1) off state vcc=13v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 0.75 1.5 2.25 3 3.75 4.5 5.25 6 iih (a) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 100 200 300 400 500 600 700 800 dvout/dt(on) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 100 200 300 400 500 600 700 800 dvout/dt(off) (v/ms) vcc=13v rl=6.5ohm
electrical specifications VND830LSP 14/27 doc id 9431 rev 4 figure 13. i lim vs t case figure 14. on-state resistance vs v cc figure 15. input high level figure 16. input hysteresis voltage figure 17. on-state resistance vs t case figure 18. input low level -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 ilim (a) vcc=13v 0 5 10 15 20 25 30 35 40 vcc (v) 0 20 40 60 80 100 120 140 160 ron (mohm) iout=2a tc=150oc tc=25oc tc= -40oc -50 -25 0 25 50 75 100 125 150 175 tc (o c ) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) iout=2a vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 1.25 1.375 1.5 1.625 1.75 1.875 2 2.125 2.25 vil (v)
VND830LSP electrical specifications doc id 9431 rev 4 15/27 figure 19. status leakage current figure 20. status low output voltage figure 21. status clamp voltage figure 22. open-load on-state detection threshold figure 23. open-load off-state voltage detection threshold -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 ilstat (a) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 iol (a) vin=5v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v
application information VND830LSP 16/27 doc id 9431 rev 4 3 application information figure 24. application schematic 3.1 gnd protection network against reverse battery this section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 solution 1: a resistor in the ground line (r gnd only) this can be used with any type of load. the following show how to dimension the r gnd resistor: 1. r gnd 600 mv / 2 (i s(on)max ) 2. r gnd ( -v cc ) / ( -i gnd ) where - i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc < 0 during reverse battery situations) is: p d = ( -v cc ) 2 / r gnd this resistor can be shared amongst several different hsds. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. v cc output2 d ld +5v r prot output1 status1 input1 +5v status2 input2 gnd +5v c r prot r prot r prot d gnd r gnd v gnd
VND830LSP application information doc id 9431 rev 4 17/27 please note that, if the microprocessor ground is not shared by the device ground, then the r gnd produces a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift varies depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then st suggests using solution 2 below. 3.1.2 solution 2: a diode (d gnd ) in the ground line a resistor (r gnd = 1 k ) should be inserted in parallel to d gnd if the device is driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network produces a shift ( 600 mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift not varies if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. 3.2 load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the v cc maximum dc rating. the same applies if the device is subject to transients on the v cc line that are greater than those shown in the iso t/r 7637/1 table. 3.3 mcu i/o protection if a ground protection network is used and negative transients are present on the v cc line, the control pins are pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the microcontroller i/o pins from latching up. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os: - v ccpeak / i latchup r prot (v oh c - v ih - v gnd ) / i ihmax example for the following conditions: v ccpeak = -100 v i latchup 20 ma v oh c 4.5 v 5k r prot 65 k . recommended values are: r prot = 10 k
application information VND830LSP 18/27 doc id 9431 rev 4 3.4 open-load detecti on in off-state off-state open-load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5 v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1) no false open-load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in th e following condition v out = (v pu / (r l + r pu ))r l < v olmin. 2) no misdetection when load is disconnected: in this case the v out has to be higher than v olmax ; this results in the following condition r pu < (v pu - v olmax ) / i l(off2) . because i s(off) may significantly increase if v out is pulled high (up to several ma), the pull- up resistor r pu should be connected to a supply that is switched off when the module is in standby. figure 25. open-load detection in off-state v ol v batt. v pu r pu r l r driver + logic + - input status v cc out ground i l(off2)
VND830LSP application information doc id 9431 rev 4 19/27 3.5 maximum demagnetization energy (v cc = 13.5 v) figure 26. maximum turn-off current versus load inductance v in , i l t demagnetization demagnetization demagnetization a = single pulse at t jstart = 150 c b= repetitive pulse at t jstart = 100 c c= repetitive pulse at t jstart = 125 c 1 10 100 0,01 0,1 1 10 100 l( mh ) i lm ax (a) a b c note: values are generated with r l = 0 . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c.
package and pcb thermal data VND830LSP 20/27 doc id 9431 rev 4 4 package and pcb thermal data 4.1 powerso-10 thermal data figure 27. powerso-10 pc board figure 28. r thj-amb vs pcb copper area in open box free air condition note: layout condition of r th and z th measurements (pcb fr4 area = 58 mm x 58 mm, pcb thickness = 2 mm, cu thickness = 35 m, copper areas: from minimum pad lay-out to 8 cm 2 ). 30 35 40 45 50 55 0246810 pcb cu heatsink area (cm^2) rthj_amb (c/w) tj-tamb=50c
VND830LSP package and pcb thermal data doc id 9431 rev 4 21/27 figure 29. thermal impedance junction ambient single pulse equation 1 : pulse calculation formula figure 30. thermal fitting model of a double channel hsd in powerso-10 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) 0.5 cm 2 6 cm 2 z th r th z thtp 1 ? () + ? = where t p t ? = t_amb pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r2 c1 c2 r1 tj_1 tj_2
package and pcb thermal data VND830LSP 22/27 doc id 9431 rev 4 table 14. thermal parameters area / island (cm 2 ) footprint 6 r1 (c/w) 0.15 r2 (c/w) 0.8 r3 (c/w) 0.7 r4 (c/w) 0.8 r5 (c/w) 12 r6 (c/w) 37 22 c1 (w.s/c) 0.0006 c2 (w.s/c) 2.1e-03 c3 (w.s/c) 0.013 c4 (w.s/c) 0.3 c5 (w.s/c) 0.75 c6 (w.s/c) 3 5
VND830LSP package and packing information doc id 9431 rev 4 23/27 5 package and packing information 5.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. 5.2 powerso-10 mechanical data figure 31. powerso-10 package dimensions detail "a" plane seating l a1 f a1 h a d d1 = = = = e4 0.10 a e c a b b detail "a" seating plane e2 10 1 eb he 0.25
package and packing information VND830LSP 24/27 doc id 9431 rev 4 table 15. powerso-10 mechanical data dim. mm min. typ. max. a 3.35 3.65 a (1) 1. muar only poa p013p. 3.4 3.6 a1 0 0.10 b 0.40 0.60 b (1) 0.37 0.53 c 0.35 0.55 c (1) 0.23 0.32 d 9.40 9.60 d1 7.40 7.60 e 9.30 9.50 e2 7.20 7.60 e2 (1) 7.30 7.50 e4 5.90 6.10 e4 (1) 5.90 6.30 e1.27 f 1.25 1.35 f (1) 1.20 1.40 h 13.80 14.40 h (1) 13.85 14.35 h0.50 l 1.20 1.80 l (1) 0.80 1.10 0 8 (1) 2 8
VND830LSP package and packing information doc id 9431 rev 4 25/27 5.3 powerso-10 packing information figure 34. powerso-10 tape and reel shipment (suffix ?tr?) figure 32. powerso-10 suggested pad layout figure 33. powerso-10 tube shipment (no suffix) 6.30 10.8 - 11 14.6 - 14.9 9.5 1 2 3 4 5 1.27 0.67 - 0.73 0. 54 - 0.6 10 9 8 7 6 b a c all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) casablanca 50 1000 532 10.4 16.4 0.8 muar 50 1000 532 4.9 17.2 0.8 c a b muar casablanca base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions
revision history VND830LSP 26/27 doc id 9431 rev 4 6 revision history table 16. document revision history date revision changes 09-sep-2004 1 initial release. 03-mar-2008 2 current and voltage convention update (page 2). configuration diagram (top view) & suggested connections for unused and n.c. pins insertion (page 2). 6 cm2 cu condition insertion in thermal data table (page 3). v cc - output diode section update (page 4). protections note insertion (page 4). revision history table insertion (page 18). disclaimers update (page 19). 09-dec-2008 3 document reformatted and restructured. added contents, list of tables and figures. added ecopack? packages information. 08-oct-2010 4 updated figure 5: switching time waveforms .
VND830LSP doc id 9431 rev 4 27/27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military , air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of VND830LSP

	To Download VND830LSP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .